1. Field of the Invention
This invention relates to a protection circuit which improves the ability of an integrated circuit to withstand electrostatic discharges (ESD), and more particularly to an ESD protection circuit for input and/or output (I/O) buffers.
2. Discussion of Background
In recent years, there has been a need to protect the input and output (I/O) pins of an integrated circuit from electrostatic damage arising, for example, from high electrostatic voltages in the handling environment. To address this problem, typically all I/Os of the integrated circuit may be required to pass specific tests which try to mimic real world conditions. One of these tests is the human body model (HBM) test in which a capacitor is charged to some large voltage, for example 2,000 volts, and then is discharged into the I/O pins of the integrated circuit through a 1.5 k ohm resistor. The other I/O pins of the integrated circuit are typically left floating, although the ground (Vss) pin may be tied to ground. During the discharge the actual voltage applied to the I/O pin does not reach the voltage across the capacitor because of the voltage drop across the 1.5 k ohm resistor. The integrated circuit may be required to withstand a minimum voltage applied to the capacitor and discharged through the 1.5 k ohm resistor without sustaining damage, which typically manifests itself as an increased leakage current on the I/O pin.
FIG. 5 is a schematic showing a four finger output pull down transistor of an integrated circuit connected to an I/O pin 20 of the integrated circuit. A complete pull down transistor circuit connected to the I/O pin 20 may consist of one or more transistors as shown in FIG. 5. In FIG. 5, the pull down transistor includes multiple fingers 40 serving as gates and connected to node N3, sources 30 connected to VSS, and drains 50 connected to an I/O pin 20 of the integrated circuit. When the ESD capacitor is charged, for example, to 2,000 volts with respect to ground, and then discharged through a 1.5 k ohm resistor into the I/O pin 20 of the integrated circuit, damage may occur to the output pull down transistor. If the pull down transistor (or single transistor device) consists of multiple fingers 40, for example, as shown in FIG. 5, the current should preferably be carried uniformly across the width of each transistor finger 40 to prevent damage during an ESD discharge.
Typically, when a high voltage (e.g., 13 volts) is applied to an I/O pin of the integrated circuit, there may be many paths by which the voltage and its associated current can be discharged to ground (note that the voltage applied to the ESD capacitor will be effectively divided across the 1.5 k ohm resistor and the on resistance of the transistor which is typically quite small, and hence the voltage at the I/O pin 20 of the integrated circuit may only reach 13 V of the 2000 V applied to the ESD capacitor). One of these paths may occur, for example, when one finger of the pull down transistor "snaps back". The term "snap back" refers to a partial breakdown across a channel region under the transistor finger and between active regions of the device. Under this condition, the transistor drain voltage decreases because the drain current increases because the apparent resistance of the channel under the transistor finger drops rapidly. The particular channel region under a specific transistor finger that breaks down first is randomly or statistically selected, depending on various process related differences produced during the manufacturing and/or fabrication of the individual transistors.
When a high voltage (e.g., 13 volts) is applied to an I/O pin 20 of the integrated circuit as a result of an ESD event, a path by which the voltage and its associated current can be discharged to VSS (ground) may be, for example, for one transistor finger 40 of a pull down transistor to "snap back" as discussed above. FIG. 6, for example, is graph of drain voltage versus drain current of a transistor finger 40 of a multi-finger device, for example as shown in FIG. 5, when a relatively high voltage is applied to the I/O pin 20 of the integrated circuit.
As shown in FIG. 6, when the transistor finger 40 "snaps back" it passes a relatively large amount of drain current from the drain 50 to the source 30 to VSS. The voltage on the I/O pin 20 of the integrated circuit is reduced from a first breakdown voltage of, for example, 13 volts to, for example, 8 volts. The transistor finger 40 snapping back appears like a resistor between the source and drain so that the drain current through the transistor finger 40 continues to increase if the drain voltage across the transistor finger 40 (i.e., on the I/O pin 20 of the integrated circuit) recovers and continues to increase, as shown in the "snapback region" in FIG. 6. Two things can happen as the drain voltage on the I/O pin 20 of the integrated circuit increases again:
a) another transistor finger 40 may snap back; or PA1 b) the snapped back transistor finger 40 may reach a second breakdown voltage and go into another even higher drain current state that may exceed its design characteristics and/or parameters, as shown in FIG. 6.
Although a transistor finger 40 of a multi-finger pull down transistor may pass a large drain current when in the snap back region of the first breakdown voltage, this drain current tends to flow evenly across the width of the transistor finger 40 from the drain to the source and is typically not destructive. In the second snap back region of the second breakdown voltage, the drain current is not uniform across the transistor finger 40 and can cause permanent damage to the integrated circuit, potentially resulting in catastrophic failure and/or excessively high leakage current during normal operation.
To prevent damage it is desirable to ensure that the first breakdown voltage of the second and subsequent fingers is triggered before the second breakdown voltage of the first finger is reached. For unsalicided technologies, the current through the snapped back finger of a multi-finger pull down transistor can be limited and controlled by the drain (and/or the source) diffusion resistance so that a large current through the resistance requires such a large voltage on the I/O pad that another of the fingers is more likely to suffer a first breakdown before the voltage across the snapped back finger rises to the second breakdown voltage. On salicided technologies, the diffusion resistance is very low and so an external resistance of, for example, polysilicon may be required between the I/O pin and each finger of the multi-finger pull down transistor to obtain the above described effect. However, large drain/source resistances may be incompatible with a relatively low output voltage when the output pull down transistor has to sink a high value of d.c. current I.sub.o in normal operation, for example, 64 mA.